1. Technical Field
The present disclosure relates to a method for manufacturing an integrated circuit comprising vias crossing a substrate, thus decreasing the thermodynamic stress in the vias, as well as the device obtained by this method.
2. Discussion
FIG. 1 illustrates an example of a three-dimensional integrated circuit.
This device comprises a first semiconductor substrate 10 having electronic components formed on its front surface 10f. In the example of FIG. 1, two MOS transistors 12 are shown at the surface of substrate 10, but it should be understood that in practice, many components are formed in substrate 10 and at the surface thereof.
Front surface 10f of substrate 10 is topped with an interconnection stack 14 comprising several interconnection levels. Each interconnection level comprises conductive tracks surrounded with insulating materials, conductive tracks of different interconnection levels being connected by conductive vias. The conductive tracks are schematically illustrated in FIG. 1.
A second semiconductor substrate 16 is also provided. On a first surface 16f of substrate 16 are formed electronic components, for example, MOS transistors 18. A stack of interconnection levels 20 extends at the surface of first surface 16f of substrate 16, and is formed of several interconnection levels comprising conductive tracks separated by insulating materials.
The two substrates 10 and 16 are positioned with respect to each other so that first surfaces 10f and 16f of each of the substrates face each other. Pads 21, respectively 22, are formed at the surface of interconnection stack 14, respectively 20. In the positioning of surfaces 10f and 16f in front of each other, pads 21 and 22 are provided to coincide. This enables to provide the bonding between the two substrates 10, 16, but also to provide an electric connection between components formed on substrate 10 and components formed on substrate 16. An insulating material 24 is generally provided to fill the space between the two interconnection stacks 14 and 20.
To form contacts on electronic components from the outside of the device of FIG. 1, vias crossing substrate 26, better known as “TSVs” (for Through-Silicon Vias) are formed in one or the other of substrates 10 and 16.
In the shown example, through vias 26 are formed in substrate 10, after thinning thereof. To for through vias 26, holes crossing the substrate are defined from rear surface 10b of substrate 10. The holes are provided to stop at the contact of conductive tracks of interconnection stack 14. A conductive track 28 is then deposited on the walls and the bottom of the holes. The space remaining in the holes is filled with a filling material 30.
As an example of numerical application, through vias may have, at the surface of substrate 10, dimensions ranging between 40 and 70 μm, and layer 28 may have a thickness ranging between 1 and 7 μm.
On the side of the second surface (rear surface 10b) of substrate 10 are formed conductive tracks 32, insulated from the outside of the device by an insulating layer 34. Such tracks allow an electric connection between the end of each through via and solder bumps 36 formed on rear surface 10b. 
To obtain the device of FIG. 1, a conventional method comprises carrying out the step of:                forming electronic components on first surfaces 10f and 16f of solid substrates 10 and 16;        forming interconnection stacks 14 and 20 of the electronic components on first surfaces 10f and 16f of substrates 10 and 16;        forming bonding and electric contact pads 21 and 22 at the surface of each of interconnection stacks 14 and 20;        arranging substrate 16 on substrate 10 via bonding and electric contact pads 21 and 22;        filling the space between stacks 14 and 20 with an insulating material 24;        thinning substrate 10;        forming holes crossing substrate 10 from rear surface 10b to access conductive tracks of interconnection stack 14;        depositing a conductive layer 28 on the walls and the bottom of the holes and forming conductive tracks on rear surface 10b of the substrate;        filling the holes with filling material 30; and        forming means of connection to the conductive tracks of surface 10b, for example, solder bumps 36.        
Conductive material 28 forming a thin layer on the walls of holes 26 currently is a metal, for example, copper. Filling material 30 currently is a polymer. The material of layer 28 and filling material 30 thus have very different expansion coefficients. For example, copper has a thermal expansion coefficient on the order of 16 ppm/° C. and the filling polymers have thermal expansion coefficients on the order of 180 ppm/° C.
FIGS. 2 and 3 illustrate a problem which occurs after the filling of the remaining volume in the through vias with material 30. More specifically, FIG. 2 schematically illustrates this problem, while FIG. 3 is an enlarged view of a real device.
To allow the deposition of filling material 30, it is generally provided to heat the structure, which implies an expansion of polymer 30. As illustrated in FIGS. 2 and 3, the difference between the thermal expansion coefficients of region 30 and those of the neighboring regions implies that, when it is returned to an ambient temperature, polymer 30 shrinks more than the neighboring regions. Thus, the shrinking of material 30 drags along the metal deposited at the bottom of hole 26, as well as, for example, a first conductive track of interconnection stack 40 (covered with an insulating material 42, in FIG. 2). These regions thus form a curved membrane.
Significant stress thus appears on conductive material 28 located on the contour of the bottom of hole 26 as well as on regions 40 and 42. The stack formed by conductive material 28, first conductive track 40, and insulating material 42 being relatively thin, there is a risk of breakage 44 in this area of the TSV. The electric connection between a contact taken from rear surface 10b of substrate 10 and conductive track 40 is then broken.
It should be noted that the above stress also appears on forming of through vias in circuits other than three-dimensional circuits and are not linked to the forming of such circuits. Especially, this type of stress may also appear in front-side illuminated image sensors of a substrate, where vias crossing the substrate are provided to create a contact from the rear surface of the substrate with tracks of an interconnection stack formed on the front surface.
Thus, there is a need for a manufacturing method limiting the risk of breakage in the materials deposited at the bottom of the holes defining through vias.